The present invention relates to a semiconductor design technology, and more particularly, to a fuse circuit for performing various circuit operations by using a fuse and a semiconductor device having the same.
Generally, with the rapid increase in the degree of integration of a semiconductor device such as a Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), several thousands to tens of thousands of memory cells are being provided in one semiconductor device. If a defect is present in any one of the memory cells, the relevant semiconductor device may not perform a desired operation. However, with the progress of processing technologies of semiconductor devices, only a small number of memory cells in a semiconductor device may be defective. Thus, it is very ineffective from the standpoint of product yield to discard a semiconductor device as a defective product due to a defect in some memory cells. To overcome this problem, a semiconductor device is further provided with redundancy memory cells, as well as normal memory cells. If a defect is present in the normal memory cells, they are replaced by redundancy memory cells for use. Hereinafter, for illustration purposes, defective memory cells among the normal memory cells that should be replaced by redundancy memory cells will be referred to as “memory cells in need of repair”.
Here, address information corresponding to the memory cells in need of repair is provided by a redundancy circuit, in which the redundancy circuit is provided with a plurality of fuses for programming address information of the memory cells in need of repair. Thus, the redundancy circuit generates address information programmed in the fuses, i.e., repair information signals. The semiconductor device compares the repair information signals with address information applied during read and write operations, and if the memory cells in need of repair are accessed, performs an operation to access the redundancy memory cells instead of the memory cells in need of repair.
For reference, an electrical cutting method, a laser cutting method, or the like is used to program the plurality of fuses provided in the redundancy circuit. The electrical cutting method is a method of applying an overcurrent to a fuse to be cut to melt and cut it, and the laser cutting method is a method of applying a laser beam to the fuse to blow and cut it. In general, the laser cutting method is widely used because it is simpler than the electrical cutting method.
Meanwhile, fuses are used to perform various operations in semiconductor device, as well as in the above-explained redundancy circuit. For example, fuses are used to tune a voltage in a constant voltage generating circuit that operates sensitively to a process, or used in various ways in a control circuit for testing or a control circuit for selecting various modes, or the like. In the following, a description will be made by taking a redundancy circuit as an example for illustration purposes.
FIG. 1 is a circuit diagram illustrating a conventional redundancy circuit.
Referring to FIG. 1, the conventional redundancy circuit includes a fuse unit 110, a latching unit 130, a precharging unit 150, and a repair information output unit 170.
The fuse unit 110 is for driving a common node COM serving as an output terminal via a current path including a fuse in response to a fuse enable signal EN_ADD<0:n> (where n is a natural number), and is provided with a plurality of fuses 112 and a plurality of activation portions 114.
The fuses 112 are for programming address information corresponding to memory cells in need of repair, and are composed of 0-th to n-th fuses F0, F1, F2, . . . , Fn. The activation portions 114 are for receiving respective fuse enable signals EN_ADD<0:n> and establishing pull-down current paths including the corresponding fuses, and are composed of 0-th to n-th NMOS transistors NM0, NM1, NM2, . . . , NMn. Here, the fuse enable signals EN_ADD<0:n> are signals generated by decoding addresses applied from the outside, and are activated correspondingly to a memory cell mat selected during read and write operations of the semiconductor device. For reference, the memory cell matrix (“MAT”) means a set of grouped memory cells among a plurality of memory cells. The 0-th to n-th fuse enable signals EN_ADD<0:n> are activated correspondingly to a memory cell mat including memory cells desired to be accessed.
The latching unit 130 is for latching a logic level value depending on the common node COM driven in response to the 0-th to n-th fuse enable signals EN_ADD<0:n>, and is provided with two inverters INV0 and INV1.
The precharging unit 150 is for setting an initial logic level value of the latching unit 130, and has a source-drain path formed between an external power supply voltage VDD terminal and the common node COM and a 0-th PMOS transistor PM0 receiving a precharging signal PCGB via the gate. Here, the precharging signal PCGB is a signal which makes a transition from logic ‘low’ to logic ‘high’ during an active operation, a read operation, or a write operation.
The repair information output unit 170 is for receiving an output signal from the latching unit 130 and outputting a repair information signal FOUT, and is provided with a second inverter INV2. Here, the repair information signal FOUT includes address information of the memory cells in need of repair that are programmed in the fuses, and the semiconductor device determines whether a memory cell desired to be accessed is a memory cell in need of repair or not in response to the repair information signal FOUT.
FIGS. 2 and 3 are timing diagrams for explaining an operation of the redundancy circuit of FIG. 1. For illustration purposes, operations of the redundancy circuit upon activation of the 0-th fuse enable signal EN_ADD<0> when the 0-th fuse F0 is cut and when the 0-th fuse F0 is not cut will be discussed.
Referring to FIGS. 1 and 2, firstly, the common node COM is precharged in response to a precharging signal PCGB of logic ‘low’, and thus the latching unit 130 latches logic ‘high’. Afterwards, the precharging signal PCGB is transited from logic ‘low’ to logic ‘high’ during an active operation, a read operation, or a write operation, and the 0-th fuse enable signal EN_ADD<0> is activated to logic ‘high’. Next, the 0-th NMOS transistor NM0 is turned on in response to the 0-th fuse enable signal EN_ADD<0>.
If the 0-th fuse F0 is not cut, a pull-down current path is formed between the common node COM and a ground power supply voltage VSS terminal. Thus, a voltage level of the common node COM becomes lower than a threshold voltage value of the 0-th inverter INV0, thereby rendering the repair information signal FOUT be logic ‘low’. Next, if the 0-th fuse F0 is cut, the common node COM is kept at logic ‘high’ by virtue of the latching unit 130. That is, since a pull-up current path is formed by the first inverter INV1, the common node COM is kept at logic ‘high’, thus rendering the repair information signal FOUT be logic ‘high’. The semiconductor device receives address information of memory cells in need of repair by using the repair information signal FOUT of logic ‘high’ or logic ‘low’.
FIG. 3 is a timing diagram for explaining a deficiency in the operation of the conventional redundancy circuit of FIG. 1. It is ideal for a fuse to have a high resistance state and a low resistance state depending on whether or not the fuse is cut, in which the corresponding operation timing is as shown in FIG. 2. That is, even if the fuse is substantially cut, the fuse may not be kept at a stable high resistance state, and even if the fuse is cut, the fuse may not be kept a stable low resistance state due to the occurrence of an abnormal phenomenon, such as a crack. In other words, the resistance state of the fuse may be less accurate.
As can be seen from FIG. 3, if the resistance state of the 0-th fuse F0 is inaccurate, even if the 0-th NMOS transistor NM0 is turned on in response to the 0-th fuse enable signal EN_ADD<0>, the common node COM does not become desired logic ‘low or ‘high’ within a predetermined time. Here, the voltage level of the common node COM and the threshold voltage VLT of the 0-th inverter INV0 have a close relation in determining the logic level of the repair information signal FOUT. Due to this, the inaccurate resistance state of the 0-th fuse F0 causes the problem of making the activation time point of the repair information signal FOUT incorrect.
Moreover, the threshold voltage VLT of the 0-th inverter INV0 may vary depending on the surrounding environment of the semiconductor device. This may act adversely in accurately determining the repair information signal FOUT depending on whether the 0-th fuse F0 is cut or not. In other words, if the 0-th fuse F0 is not cut, the repair information signal FOUT may be outputted wrongly as logic ‘high’, or if the 0-th fuse F0 is cut, the repair information signal FOUT may be outputted wrongly as logic ‘low’. That is, the reliability of the repair information signal FOUT is deteriorated, which may cause a malfunction in the repair operation of the semiconductor device.